Synopsys Design — Compiler Tutorial 2021

report_power > reports/power.rpt

Write the gate-level Verilog.

In 2021, the .synopsys_dc.setup file is read from three locations (install, home, local). Create one in your working directory. synopsys design compiler tutorial 2021

# Set operating condition (Slow corner for setup timing checks) set_operating_conditions -max tsmc65nm_ss_0v9_125c # Instruct the tool to make the design as small as possible set_max_area 0 Use code with caution. 5. Synthesis and Optimization Strategies

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: Reads your Verilog or VHDL files and checks for syntax errors.

# Basic compilation compile

With low-power design being ubiquitous, DC supports UPF for defining power domains, isolation cells, and level shifters.

# Create clean work directory file mkdir WORK define_design_lib WORK -path ./WORK # Analyze HDL files for syntax errors analyze -format verilog my_alu.v control_unit.v top_module.v # Elaborate the top-level architecture elaborate top_module # Set current design context current_design top_module # Verify that the design links correctly with libraries link Use code with caution. 4. Defining Design Constraints # Set operating condition (Slow corner for setup

# External device takes 2ns after clock edge to launch data into your input port set_input_delay -max 2.0 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] # External device requires data 1.5ns before the next clock edge at your output port set_output_delay -max 1.5 -clock sys_clk [all_outputs] Use code with caution. Environment Modeling